Welcome to Howard Ho's website.

My Experience

• GPU Performance and Power Engineer at NVIDIA Corporation – January 2023 onwards: My responsibilities include: - Optimizing for improved performance per watt for our NVIDIA GPUs on a variety of workloads tailored to different potential users/use cases on mobile vs. desktop vs. server. - Characterizing power consumption and measuring performance scores for representative applications and scenarios. - Performing competitive analysis for power and performance across our competitors' GPU models and platforms; collecting and computing data needed to perform a comprehensive comparison and draw conclusions. - Working with cross-functional teams to determine, collect and share requested power and performance data for various analysis/purposes. - Supporting and improving our internal automation framework for test execution and data collection.
• Software and System Validation Engineer at Intel Corporation – June 2022 to January 2023: My work encompasses pre-/post-silicon: virtual platform simulation and FPGA emulation (Simics), as well as real hardware (ES/QS samples) to ensure our CPUs meet or exceed our customers’ specifications and use cases. I define validation strategies and develop comprehensive test suites, scripts, and debug hooks to validate server networking product subsystems and platforms integrated into Intel Xeon processor SoCs across multiple roadmaps, from pre-silicon models to post-silicon development hardware. I then collect findings from these tests run in simulation or actual hardware to discover issues efficiently at the RTL, firmware, platform integration and/or specification level(s). Subsequently, I drive resolutions of sightings filed from these findings/observations. I also apply a broad understanding of system architecture and debug techniques to work closely with cross-functional pre-/post-silicon engineers from cross-site architecture, design, software, and emulation teams on a regular basis for supporting a wide range of Network Data Accelerator IPs and platform hardware applications (such as 4G and 5G VRAN). Additionally, I apply general platform integration and debugging expertise across a range of debug interfaces (JTAG, DCI and ITH among other internal interfaces) using various new technologies to architect, define, and develop test strategies that identify testing gaps and new validation areas to expand the testing scope for upcoming future products. Finally, I discuss, architect, implement, support and extend various internal software tools and automation scripts (written in C, C++, Python, batch/Tcl script etc.) to enhance focus and stress test case coverage. All along this process, I also help create unified lab automation architecture for easy environment setup flow with minimal manual interaction required on lab host systems.
• SoC Power Validation Engineer at Apple Inc. – June 2021 to June 2022: I engaged in power hardware validation and analysis of typical SoC workloads, such as video streaming/recording, by measuring silicon power dissipation of these workloads, then analyzing the collected data to correlate measurements with simulation or projection results. My analysis of these workloads and their power dissipation helped drive power optimization efforts to achieve best-in-class power and performance for our state-of-the-art ASICs. To accomplish this, I collaborated with colleagues across various teams such as design, architecture, systems, and software teams to enable use-case power measurements, and tuned hardware and software settings to improve energy efficiency, thus playing a strategic role in getting functional products to millions of customers quickly. Finally, I also assisted in improving our power measurement infrastructure.
• SSD Validation Engineer Intern at Intel Corporation – June 2020 to December 2020: I was an SSD Validation Engineer Intern in the Non-Volatile Memory Solutions Group at Intel for summer and fall 2020 (7 months). I worked with a team of engineers in planning tests to validate SSD features and debug SSD firmware or hardware issues that are discovered by running these tests. I also worked alongside other teams such as the firmware, security, testing framework and ASIC/FPGA design teams to help troubleshoot and root cause these issues. I ran SSD testing on a wide variety of hardware platforms involving both client and server motherboards. The tests ran included benchmarking, FIO workloads, data integrity tests, LTSSM link training tests, and NVMe compliance suite testing. The tests were run on both Linux and Windows OSes. In addition, different BIOS configurations and versions were used with each motherboard model. Tests were scripted to use Bash shell on Linux and PowerShell/Command Prompt on Windows. All these were done to ensure there were no compatibility issues. I then had to report my findings from these tests to our team, and if issues arose, I contacted and worked with teams to direct the implementation of solutions to solve these issues.
• Academic Intern for Machine Structures (CS 61C) – August 2019 to December 2019 (Fall 2019): As an academic intern and lab assistant, I helped students to solve the problems they encountered when they did the assignments. I answered or clarified the concepts they were confused or not sure so that they could be well prepared for the tests or examinations. I assisted the TA in leading discussions, and guiding, monitoring and grading lab exercises. By doing so, I gained a deeper understanding of the course material (C, Google Go language, RISC-V Assembly, and Logisim), engaged with students, and got valuable teaching experience. Additionally, I completed weekly reflections about the experience of helping the students and the ways I used to make them better understand the concepts.
• Academic Intern for Data Structures (CS 61B) – January 2019 to May 2019 (Spring 2019): As an academic intern and lab assistant, I helped students to solve the problems they encountered when they did the assignments. I answered or clarified the concepts they were confused or did not understand so that they could be well prepared for the tests or examinations. I assisted the TA in leading discussions, and guiding, monitoring and grading lab exercises. Being an AI, I gained a deeper understanding of the course material (Java) and got valuable teaching experience.